Silicom’s 10 Gigabit Ethernet PCI Express server adapters are designed for Servers and high-end appliances.

The Silicom 10 Gigabit Ethernet PCI Express NICs offer simple integration into any PCI Express X8 to 10Gigabit Networks. The performance is optimized so that system I/O is not the bottleneck in high-performance networking applications.

The Silicom 10 Gigabit Ethernet PCI Express server adapters are based on Intel 82599ES Ethernet controller with two fully integrated Gigabit Ethernet Media Access Control (MAC) and SFI ports.

In addition to managing MAC and PHY Ethernet layer functions, the controller manages PCI Express packet traffic across its transaction, link, and physical/logical layers. Using hardware acceleration, the controller offloads tasks from the host, such as TCP/UDP/IP checksum calculations and TCP segmentation.

Silicom’s 10 Gigabit Ethernet PCI-Express Server adapters are the ideal solution for implementing multiple network segments, mission-critical high-powered networking applications and environments within high performance servers.

SFP+ 10Gigabit Ethernet:

10Gigabit Ethernet Adapter with SFP cage support:

Copper 10SFP+Cu (Passive Direct Attach Cable):

• Compliant with the SFP+ MSA SFF-8431 specification
• Up to 10 meters

Fiber 10 Gigabit Ethernet 10GBASE-SR:

• 10BASE-SR with 10Gigabit 850nM Small form Factor Pluggable (SFP+)

Fiber 10 Gigabit Ethernet 10GBASE-LR:

• 10BASE-LR with 10Gigabit 1310nM Small form Factor Pluggable (SFP+)

Host Interface:

• PCI Express X8 lanes
• Support PCI Express Base Specification 3.0 (8GT/sec)
• Low power

Performance Features:

• IPV4 and IPV6 Supports for IP/ TCP and IP/UDP Receive Checksum offload
• Fragmented UDP checksum offload for Packet Reassembly
• CPU utilization- the 82599 supports reduction in CPU utilization, mainly by supporting Receive Side Coalescing (RSC)
• Support for 16 virtual machine Device Queues (VMDq) per port
• Support Direct Cache Access (DCA)
• Advanced memory architecture reduces latency by preceding TSO packets. A TSO packet may be interleaved with other packets going to the wire
• Minimized device I/O intterupts using MSI and MSI-X
• Offload of TCP / IP / UDP checksum calculation and TCP segmentation
• Large on chip receive packet buffer (512 KB)
• Large on chip transmit packet buffer (160KB)
• Supports the VPD (Vital Product Data) capability defined in the PCI specification ver. 3.0
• Time sync- IEEE1588- Precision Time Protocol (PTP)
• Supports the BCN (Backward Congestion Notification) protocol in addition to the EEDC functionality

LAN Features:

• IEEE 802.x flow control support
• IEEE 802.q VLAN tagging support
• Supports a mode where all received and sent packets have at least one VLAN tag in addition to the regular tagging
• IEEE 802.1p layer 2 priority encoding
• Jumbo Frame (up to 15.5KB)
• Link Aggregation and Load Balancing
• RFC2819 RMON MIB statistics
• TCP Segmentation Offload Up to 256KB
• Ipv6 Support for IP/TCP Receive Checksum Offload
• DDP Offload
• LEDs indicators for link/Activity and speed

Security Features:

• IEEE P802.1AE LinkSec specification. It incorporates an inline packet crypto unit to support both privacy and integrity checks on a packet by packet basis. The transmit data path includes both encryption and signing engines. On the receive data path it includes both decryption and integrity checkers
• IPsec off load for a given number of flows
• Off-load IPsec for up to 1024 Security associations (SA) for each of TX and RX
• AH and ESP protocols for authentication and encryption
• AES-128-GMAC and AES-GCM crypto engines
• Transport mode encapsulation

Specifications: